Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
F
FFmpeg
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Container Registry
Model registry
Operate
Environments
Monitor
Incidents
Service Desk
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
libremedia
Tethys
FFmpeg
Commits
e5c2794a
Commit
e5c2794a
authored
12 years ago
by
Janne Grunau
Browse files
Options
Downloads
Patches
Plain Diff
x86: consistently use unaligned movs in the unaligned bswap
Fixes fate errors in asv1, ffvhuff and huffyuv on x86_32.
parent
fdaacc59
No related branches found
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
libavcodec/x86/dsputil.asm
+6
-6
6 additions, 6 deletions
libavcodec/x86/dsputil.asm
with
6 additions
and
6 deletions
libavcodec/x86/dsputil.asm
+
6
−
6
View file @
e5c2794a
...
@@ -552,8 +552,8 @@ VECTOR_CLIP_INT32 6, 1, 0, 0
...
@@ -552,8 +552,8 @@ VECTOR_CLIP_INT32 6, 1, 0, 0
%if cpuflag(ssse3)
%if cpuflag(ssse3)
pshufb
m0
,
m2
pshufb
m0
,
m2
pshufb
m1
,
m2
pshufb
m1
,
m2
mov
a
[
r0
+
0
],
m0
mov
%
1
[
r0
+
0
],
m0
mov
a
[
r0
+
16
],
m1
mov
%
1
[
r0
+
16
],
m1
%else
%else
pshuflw
m0
,
m0
,
10110001b
pshuflw
m0
,
m0
,
10110001b
pshuflw
m1
,
m1
,
10110001b
pshuflw
m1
,
m1
,
10110001b
...
@@ -567,8 +567,8 @@ VECTOR_CLIP_INT32 6, 1, 0, 0
...
@@ -567,8 +567,8 @@ VECTOR_CLIP_INT32 6, 1, 0, 0
psrlw
m3
,
8
psrlw
m3
,
8
por
m2
,
m0
por
m2
,
m0
por
m3
,
m1
por
m3
,
m1
mov
a
[
r0
+
0
],
m2
mov
%
1
[
r0
+
0
],
m2
mov
a
[
r0
+
16
],
m3
mov
%
1
[
r0
+
16
],
m3
%endif
%endif
add
r0
,
32
add
r0
,
32
add
r1
,
32
add
r1
,
32
...
@@ -581,7 +581,7 @@ VECTOR_CLIP_INT32 6, 1, 0, 0
...
@@ -581,7 +581,7 @@ VECTOR_CLIP_INT32 6, 1, 0, 0
mov
%
1
m0
,
[
r1
]
mov
%
1
m0
,
[
r1
]
%if cpuflag(ssse3)
%if cpuflag(ssse3)
pshufb
m0
,
m2
pshufb
m0
,
m2
mov
a
[
r0
],
m0
mov
%
1
[
r0
],
m0
%else
%else
pshuflw
m0
,
m0
,
10110001b
pshuflw
m0
,
m0
,
10110001b
pshufhw
m0
,
m0
,
10110001b
pshufhw
m0
,
m0
,
10110001b
...
@@ -589,7 +589,7 @@ VECTOR_CLIP_INT32 6, 1, 0, 0
...
@@ -589,7 +589,7 @@ VECTOR_CLIP_INT32 6, 1, 0, 0
psllw
m0
,
8
psllw
m0
,
8
psrlw
m2
,
8
psrlw
m2
,
8
por
m2
,
m0
por
m2
,
m0
mov
a
[
r0
],
m2
mov
%
1
[
r0
],
m2
%endif
%endif
add
r1
,
16
add
r1
,
16
add
r0
,
16
add
r0
,
16
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment