From 37961044c6cc633c28d87293775d8e985d156921 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Storsj=C3=B6?= <martin@martin.st>
Date: Sun, 17 Jul 2016 13:31:06 +0300
Subject: [PATCH] checkasm: arm: Ignore changes to bits 0-4 and 7 of FPSCR
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These bits are set by exceptions in NEON instructions.
Also print the differing bits when FPSCR is clobbered,
and use bic instead of lsl, for clearing the topmost bits.
Signed-off-by: Martin Storsjö <martin@martin.st>
---
tests/checkasm/arm/checkasm.S | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tests/checkasm/arm/checkasm.S b/tests/checkasm/arm/checkasm.S
index 2768bb3e74a..ab53d0ac066 100644
--- a/tests/checkasm/arm/checkasm.S
+++ b/tests/checkasm/arm/checkasm.S
@@ -40,7 +40,7 @@ const register_init, align=3
endconst
const error_message_fpscr
- .asciz "failed to preserve register FPSCR"
+ .asciz "failed to preserve register FPSCR, changed bits: %x"
error_message_gpr:
.asciz "failed to preserve register r%d"
error_message_vfp:
@@ -106,11 +106,13 @@ function checkasm_checked_call_\variant, export=1
.endr
.purgem check_reg_vfp
- fmrx r0, FPSCR
+ fmrx r1, FPSCR
ldr r3, [sp, #8]
- eor r0, r0, r3
+ eor r1, r1, r3
+ @ Ignore changes in bits 0-4 and 7
+ bic r1, r1, #0x9f
@ Ignore changes in the topmost 5 bits
- lsls r0, r0, #5
+ bics r1, r1, #0xf8000000
bne 3f
.endif
--
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